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STK20C04
STK20C04
CMOS nvSRAM High Performance 512 x 8 Nonvolatile Static RAM
FEATURES
* * * * * * * * * * * * * 30, 35 and 45ns Access Times 15, 20 and 25ns Output Enable Access Unlimited Read and Write to SRAM Hardware STORE Initiation Automatic STORE Timing 105 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Hardware RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5V10% Operation Commercial and Industrial Temperatures Available in 600 mil PDIP package
DESCRIPTION
The Simtek STK20C04 is a fast static RAM (30, 35, 45ns), with a nonvolatile electrically-erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data may easily be transferred from the SRAM to the EEPROM (STORE), or from the EEPROM to the SRAM (RECALL) using the NE pin. It combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. The STK20C04 features the industry standard pinout for nonvolatile RAMs in a 28-pin 600 mil plastic DIP.
LOGIC BLOCK DIAGRAM
EEPROM ARRAY 64 X 64 STORE
ROW DECODER
PIN CONFIGURATIONS
NE NC A7 A
6 5 4 3 2 1 0 0 1 2 14 15 6 7 8 9 10 11 12 13 23 22 21 20 19 18 17 16 1 2 3 4 5 28 27 26 25 24
V CC W NC A
8
A3 A4 A5 A6 A7 A8 STATIC RAM ARRAY 64 X 64
RECALL
A A A A A A DQ DQ DO
NC NC G NC E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
VSS
28 - 600 PDIP
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 E W INPUT BUFFERS COLUMN I/O STORE/ RECALL CONTROL
COLUMN DECODER
PIN NAMES
A0 - A8 W DQ0 - DQ7
G NE
Address Inputs Write Enable Data In/Out Chip Enable Output Enable Nonvolatile Enable Power (+5V) Ground
A0
A1
A2
E G NE VCC VSS
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STK20C04 ABSOLUTE MAXIMUM RATINGS a
Voltage on typical input relative to VSS. . . . . . . . . . . . . -0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .-0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
(One output at a time, one second duration)
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC b
1
(VCC = 5.0V 10%)
INDUSTRIAL MIN MAX 85 80 75 50 30 27 23 1 1 5 2.2 VSS-.5 2.4 0.4 0 70 -40 0.4 85 VCC+.5 0.8 UNITS mA mA mA mA mA mA mA mA A A V V V V C tAVAV = 30ns tAVAV = 35ns tAVAV = 45ns All inputs at VIN 0.2V or (VCC - 0.2V) 27 23 20 tAVAV = 30ns tAVAV = 35ns tAVAV = 45ns E VIH; all others cycling E (VCC - 0.2V) all others VIN 0.2V or (VCC - 0.2V) 1 5 2.2 VSS-.5 2.4 VCC+.5 0.8 VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC All Inputs All Inputs IOUT = -4mA IOUT = 8mA NOTES MIN MAX 80 75 65
PARAMETER Average VCC Current
ICC d
2
Average VCC Current during STORE cycle Average VCC Current (Standby, Cycling TTL Input Levels)
50
ISB c
1
ISB c
2
Average VCC Current (Standby, Stable CMOS Input Levels) Input Leakage Current (Any Input) Off State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
1
IILK IOLK VIH VIL VOH VOL TA
Note b: ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: ICC 2 is the average current required for the duration of the store cycle (t STORE) after the sequence (tWC) that initiates the cycle.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Output 5.0V
480 Ohms
CAPACITANCE (TA=25C, f=1.0MHz)e
255 Ohms
SYMBOL CIN COUT
PARAMETER Input Capacitance Output Capacitance & W
MAX 7 7
UNITS pF pF
CONDITIONS V = 0 to 3V V = 0 to 3V
30pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
2-40
STK20C04 READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 11A Note c: Note e: Note f: Note g: Note h: #1, #2 tELQV tAVAVR tAVQV tGLQV tAXQX tELQX tEHQZi tGLQX tGHQZ
i e c,e h g
(VCC = 5.0V 10%)
STK20C04-30 STK20C04-35 MIN MAX 35 35 30 15 5 5 18 0 18 0 25 35 0 25 45 0 20 0 25 55 5 5 20 0 25 35 20 5 5 25 45 45 25 STK20C04-45 MIN MAX 45 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MIN MAX 30 30
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWR
PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Write Recovery Time
tELICCH tEHICCL tWHQV
Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Parameter guaranteed but not tested. NE must be high during entire cycle. For READ CYCLE #1 and #2, W and NE must be high for entire cycle. Device is continuously selected with E low and G low.
Note i: Measured 200mV from steady state output voltage.
READ CYCLE #1 f,g,h
2 tAVAVR ADDRESS 5 3 tAVQV
DATA VALID
tAXQX DQ (Data Out)
W
11A tWHQV
READ CYCLE #2 f,g
2 tAVAVR ADDRESS 1 tELQV 11 tEHICCL 7 tEHQZ 9 tGHQZ
DATA VALID
E
tELQX 4 tGLQV 8 tGLQX
6
G
DQ (Data Out) tELICCH ICC ACTIVE STANDBY 10
W
11A tWHQV
2-41
STK20C04 WRITE CYCLES #1 & #2
SYMBOLS NO. 12 13 14 15 16 17 18 19 20 21 Note f: #1 tAVAVW tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ
i,m
(VCC = 5.0V 10%)
STK20C04-30 STK20C04-35 MIN 45 35 35 30 0 35 0 0 35 5 5 35 5 MAX STK20C04-45 MIN 45 35 35 30 0 35 0 0 35 MAX UNITS ns ns ns ns ns ns ns ns ns ns PARAMETER MIN 45 35 35 30 0 35 0 0 MAX
#2 tAVAVW tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
#3 tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold After End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write
tWHQX
NE must be high during entire cycle.
Note i: Measured 200mV from steady state output voltage. Note k: E or W must be high during address transitions. Note m: If W is low when E goes low, the outputs remain in the high impedance state.
WRITE CYCLE #1: W CONTROLLED f,k
12 tAVAVW ADDRESS 14 tELWH E 18 17 tAVWH 19 tWHAX
tAVWL W
13 tWLWH 15 tDVWH 16 tWHDX
DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA
DATA VALID
21 tWHQX
HIGH IMPEDANCE
WRITE CYCLE #2: E CONTROLLED f,k
12 tAVAVW ADDRESS 18 tAVEL E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN
DATA VALID
14 tELEH
19 tEHAX
16 tEHDX
DATA OUT
HIGH IMPEDANCE
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STK20C04
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X MODE Not Selected Read RAM Write RAM Nonvolatile RECALLn Nonvolatile STORE No operation POWER Standby Active Active Active ICC
2
Active
STORE CYCLES #1 & #2
SYMBOLS NO. 22 23 24 25 26 27 28 tNLWL tELWL tWLEL #1 tWLQXp tWLNH
q
(VCC = 5.0V 10%)
PARAMETER MIN MAX 10 45 0 0 0 0 0 UNITS ms ns ns ns ns ns ns
#2 tELQXS tELNHS
Alt. tSTORE tWC
STORE Cycle Time STORE Initiation Cycle Time
Output Disable Set-up to NE Fall
tGHNL tGHEL tNLEL
Output Disable Set-up to E Fall NE Set-up Chip Enable Set-up Write Enable Set-up
Note: n: An automatic RECALL also takes place at power up, starting when VCC exceeds 3.8V, and taking tRECALL from the time at which VCC exceeds 4.5V. VCC must not drop below 3.8V once it has exceeded it for the RECALL to function properly. Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated. Note p: Measured with W and NE both returned high, and G returned low. Note that STORE cycles are inhibited/aborted by VCC < 3.8V (STORE inhibit). Note q: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle.
STORE CYCLE #1: W CONTROLLEDo
NE
G W
24 tGHNL 27 tELWL
26 tNLWL
23 tWLNH
E
DQ (Data Out)
HIGH IMPEDANCE
22 tWLQX
STORE CYCLE #2: E CONTROLLEDo
NE 25 tGHEL G W E 28 tWLEL 23 tELNHS 22 tELQXS 26 tNLEL
DQ (Data Out)
HIGH IMPEDANCE
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STK20C04 RECALL CYCLES #1, #2 & #3
SYMBOLS NO. 29 30 31 32 33 34 35 tGLNL tWHNL tELNL tNLQZ #1 tNLQXr tNLNH
s
(VCC = 5.0V 10%)
MIN MAX 20 25 0 0 0 0 25 UNITS s ns ns ns ns ns
#2 tELQXR tELNHR tNLEL tGLEL tWHEL
Alt. tGLQXR tGLNH tNLGL
PARAMETER
RECALL Cycle Time RECALL Initiation Cycle Time
NE Set-up Output Enable Set-up
tWHGL tELGL
t
Write Enable Set-up Chip Enable Set-up NE Fall to Outputs Inactive
ns Note r: Measured with W and NE both high, and G and E low. Note s: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the
RECALL initiation cycle. Note t: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE CONTROLLED o
NE 32 tGLNL 30 tNLNH
G
W E
33 tWHNL
34 tELNL DQ (Data Out)
tNLQZ
35
29 tNLQX
HIGH IMPEDANCE
RECALL CYCLE #2: E CONTROLLEDo
NE G 32 tGLEL 33 tWHEL W E 30 tELNHR 29 tELQXR 31 tNLEL
DQ (Data Out)
HIGH IMPEDANCE
RECALL CYCLE #3: G CONTROLLEDo,t
31 tNLGL NE G 33 tWHGL W E 34 tELGL 29 tGLQXR 30 tGLNH
DQ (Data Out)
HIGH IMPEDANCE
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STK20C04
DEVICE OPERATION
The STK20C04 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the memory operates as an ordinary static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. and output is disabled and the DQ0-7 pins are tri-stated until the cycle is completed. If E and G are LOW and W and NE are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE.
SRAM READ
The STK20C04 performs a READ cycle whenever E and G are LOW and NE and W are HIGH. The address specified on pins A0-8 determines which of the 512 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at t ELQV or at tGLQV whichever is later (READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or NE is brought LOW.
HARDWARE PROTECT
The STK20C04 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W, and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the STK20C04 offers hardware protection through V CC Sense. A STORE cycle will not be initiated, and one in progress will discontinue if V CC goes below 3.8V. 3.8V is a typical, characterized value.
NONVOLATILE RECALL
A RECALL cycle is performed when E, G, and NE are LOW and W is HIGH. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on any control pin to cause a recall, preventing inadvertent multi-triggering. On power-up, once V CC exceeds the VCC sense voltage of 3.8V, a RECALL cycle is automatically initiated. The voltage on the V CC pin must not drop below 3.8V once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until t NLQX after VCC exceeds 3.8V. 3.8V is a typical, characterized value.
SRAM WRITE
A write cycle is performed whenever E and W are LOW and NE is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W are LOW and G is HIGH. While any sequence to achieve this state will initiate a STORE, only W initiation (STORE CYCLE #1) and E initiation (STORE CYCLE #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input
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STK20C04
ORDERING INFORMATION
STK20C04 - W 30 I Temperature Range
blank = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C)
Access Time
30 = 30ns 35 = 35ns 45 = 45ns
Package
W = Plastic 28 pin 600 mil DIP
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